Browsing articles tagged with " vhdl"
Digital Systems CW2: Stopwatch
C – micro
#include <reg66x.h>
/////////////////////////
//// PIN DEFINITIONS ////
/////////////////////////
// Port 0 - in - in from CPLD
#define inDigits P0
// Port 1 - all out - out to CPLD
sbit outClock = P1^0;
sbit outReset = P1^1;
// Port 2 - all out - out to display
#define outDisplay P2
// Port 3 - in/out - buttons & speaker & CPLD control
sbit btnStartStop = P3^3; // in
sbit outAcknowledge = P3^7;// out
/////////////////////////////
//// DECLARE SUBROUTINES ////
/////////////////////////////
void setupTimer();
void setupInputs();
void runningLoop();
void timerCallback();
void digitsCallback();
void controlCallback();
void resetCPLD();
///////////////////////////
//// DECLARE VARIABLES ////
///////////////////////////
int modeState = 0;
unsigned char hunths, tenths, seconds, tenSecs;
////////////////////////
//// PROGRAMME CODE ////
////////////////////////
void main() {
setupTimer();
setupInputs();
resetCPLD();
runningLoop();
}
void runningLoop() {
while(1){
outDisplay = tenSecs + 64;
outDisplay = seconds + 128;
outDisplay = tenths + 192;
outDisplay = hunths + 0;
}
}
void resetCPLD(){
outReset = 1;
outReset = 0;
return;
}
void setupTimer() {
TMOD = 0x01; // M0 = 1 (Timer mode 1 - 16 bit mode)
TL0 = 0xFF; // 400Hz = 2304 delay count, 65535-2304 = 63231
TH0 = 0xF6; // TH0 = 0xF6 :: TL0(0xFF) = 0xF6FF = 63231
ET0 = 1; // T0 Interrupt enabled.
EA = 1; // Interrupts enabled.
TR0 = 1; // Begin timer.
P2 = 0x00000000;
return;
}
void setupInputs() {
EA = 1; // Interrupts enabled.
IT0 = 1; // Set on falling edge.
IT1 = 1; // Set on falling edge.
EX0 = 1; // Enable external interrupt 0.
EX1 = 1; // Enable external interrupt 1.
modeState = 0;
outAcknowledge = 0;
return;
}
//////// INTERRUPT CALLBACKS ////////
void timerCallback() interrupt 1 using 2 {
TR0 = 0;
TL0 = 0xFF; // 400Hz = 2304 delay count, 65535-2304 = 63231
TH0 = 0xF6; // TH0 = 0xF6 :: TL0(0xFF) = 0xF6FF = 63231
TF0 = 0;
TR0 = 1; // Begin timer.
outClock =~ outClock; // Invert the clock output pin.
}
void digitsCallback() interrupt 0 {
if(modeState == 0){
seconds = inDigits & 0x0f;
}else if(modeState == 1){
tenSecs = inDigits & 0x0f;
}else if(modeState == 2){
hunths = inDigits & 0x0f;
}else if(modeState == 3){
tenths = inDigits & 0x0f;
}
if(modeState < 3){
modeState++;
}else{
modeState = 0;
}
outAcknowledge = 1;
outAcknowledge = 0;
}
void controlCallback() interrupt 2 {
TR0 =~ TR0;
}
VHDL – CPLD
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:25:53 03/18/2009
-- Design Name:
-- Module Name: clock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clock is
Port ( clockSource : in STD_LOGIC; -- clock pulse from micro
reset : in STD_LOGIC; -- reset pulse from micro
microAck : in STD_LOGIC; -- acknowledgement from micro
digit : out STD_LOGIC_VECTOR (3 downto 0);
-- numbers to micro
cpldRts : out STD_LOGIC); -- ready to send to micro (ACTIVE LOW)
end clock;
architecture Behavioral of clock is
signal hunthsCount : std_logic_vector(3 downto 0);
signal tenthsCount : std_logic_vector(3 downto 0);
signal secondCount : std_logic_vector(3 downto 0);
signal tenSecCount : std_logic_vector(3 downto 0);
signal controlFlag : std_logic_vector(1 downto 0);
begin
process(reset, clockSource)
begin
if reset = '1' then
hunthsCount
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