Digital Systems CW2: Stopwatch

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C – micro

#include 

/////////////////////////
//// PIN DEFINITIONS ////
/////////////////////////

// Port 0 - in - in from CPLD
#define inDigits P0

// Port 1 - all out - out to CPLD
sbit outClock = P1^0;
sbit outReset = P1^1;

// Port 2 - all out - out to display
#define outDisplay P2

// Port 3 - in/out - buttons & speaker & CPLD control
sbit btnStartStop = P3^3;  // in
sbit outAcknowledge = P3^7;// out

/////////////////////////////
//// DECLARE SUBROUTINES ////
/////////////////////////////

void setupTimer();
void setupInputs();
void runningLoop();
void timerCallback();
void digitsCallback();
void controlCallback();
void resetCPLD();

///////////////////////////
//// DECLARE VARIABLES ////
///////////////////////////

int modeState = 0;
unsigned char hunths, tenths, seconds, tenSecs;

////////////////////////
//// PROGRAMME CODE ////
////////////////////////

void main() {
    setupTimer();
    setupInputs();
    resetCPLD();
   runningLoop();
}

void runningLoop() {
    while(1){
        outDisplay = tenSecs + 64;
        outDisplay = seconds + 128;
        outDisplay = tenths + 192;
        outDisplay = hunths + 0;
    }
}

void resetCPLD(){
    outReset = 1;
    outReset = 0;

    return;
}

void setupTimer() {
    TMOD = 0x01;        // M0 = 1 (Timer mode 1 - 16 bit mode)
    TL0 = 0xFF;         // 400Hz = 2304 delay count, 65535-2304 = 63231
    TH0 = 0xF6;         // TH0 = 0xF6 :: TL0(0xFF) = 0xF6FF = 63231
    ET0 = 1;                // T0 Interrupt enabled.
    EA = 1;             // Interrupts enabled.
    TR0 = 1;                // Begin timer.

    P2 = 0x00000000;

    return;
}

void setupInputs() {
    EA = 1;             // Interrupts enabled.
    IT0 = 1;                // Set on falling edge.
    IT1 = 1;                // Set on falling edge.
    EX0 = 1;            // Enable external interrupt 0.
    EX1 = 1;                // Enable external interrupt 1.

    modeState = 0;
    outAcknowledge = 0;

    return;
}

//////// INTERRUPT CALLBACKS ////////

void timerCallback() interrupt 1 using 2 {
   TR0 = 0;
    TL0 = 0xFF;         // 400Hz = 2304 delay count, 65535-2304 = 63231
    TH0 = 0xF6;         // TH0 = 0xF6 :: TL0(0xFF) = 0xF6FF = 63231
    TF0 = 0;
    TR0 = 1;                // Begin timer.
    outClock =~ outClock;   // Invert the clock output pin.
}

void digitsCallback() interrupt 0 {
    if(modeState == 0){
        seconds = inDigits & 0x0f;
    }else if(modeState == 1){
        tenSecs = inDigits & 0x0f;
    }else if(modeState == 2){
        hunths = inDigits & 0x0f;
    }else if(modeState == 3){
        tenths = inDigits & 0x0f;
    }

    if(modeState < 3){
        modeState++;
    }else{
        modeState = 0;
    }

    outAcknowledge = 1;
    outAcknowledge = 0;
}

void controlCallback() interrupt 2 {
    TR0 =~ TR0;
}

VHDL - CPLD

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    12:25:53 03/18/2009
-- Design Name:
-- Module Name:    clock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clock is
    Port ( clockSource : in STD_LOGIC;  -- clock pulse from micro
           reset : in  STD_LOGIC;        -- reset pulse from micro
           microAck : in STD_LOGIC;      -- acknowledgement from micro
              digit : out  STD_LOGIC_VECTOR (3 downto 0);
                                                      -- numbers to micro
              cpldRts : out STD_LOGIC);     -- ready to send to micro (ACTIVE LOW)
end clock;

architecture Behavioral of clock is

signal hunthsCount : std_logic_vector(3 downto 0);
signal tenthsCount : std_logic_vector(3 downto 0);
signal secondCount : std_logic_vector(3 downto 0);
signal tenSecCount : std_logic_vector(3 downto 0);
signal controlFlag : std_logic_vector(1 downto 0);

begin                                                         

process(reset, clockSource)
begin
if reset = '1' then
    hunthsCount <= "0000";
    tenthsCount <= "0000";
    secondCount <= "0000";
    tenSecCount <= "0000";
    controlFlag <= "10";
    cpldRts <= '1';
elsif microAck = '1' then
    cpldRts <= '1';
elsif clockSource'event and clockSource = '1' then

    if controlFlag = "00" then
        digit <= hunthsCount;
        controlFlag <= "01";
        cpldRts <= '0';

    elsif controlFlag = "01" then
        digit <= tenthsCount;
        controlFlag <= "10";
        cpldRts <= '0';

    elsif controlFlag = "10" then
        digit <= secondCount;
        controlFlag <= "11";
        cpldRts <= '0';

    elsif controlFlag = "11" then
        digit <= tenSecCount;
        controlFlag <= "00";
        cpldRts <= '0';

        if hunthsCount <= "1000" then
            hunthsCount <= hunthsCount + "1";

        else
            hunthsCount <= "0000";

            if tenthsCount <= "1000" then
                tenthsCount <= tenthsCount + "1";

            else
                tenthscount <= "0000";

                if secondCount <= "1000" then
                    secondCount <= secondCount + "1";

                else
                    secondCount <= "0000";

                    if tenSecCount <= "1000" then
                        tenSecCount <= tenSecCount + "1";

                    else
                        tenSecCount <= "0000";

                    end if;
                end if;
            end if;
        end if;
    end if;

end if;
end process;

end Behavioral;

VHDL Testbench

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:   11:29:08 03/25/2009
-- Design Name:   clock
-- Module Name:   N:/Coursework/DigitalSystemS2/stopwatch/vhdl/counter_testbench.vhd
-- Project Name:  vhdl
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: clock
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY counter_testbench_vhd IS
END counter_testbench_vhd;

ARCHITECTURE behavior OF counter_testbench_vhd IS 

    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT clock
    PORT(
        clockSource : IN std_logic;
        reset : IN std_logic;
        digit : OUT std_logic_vector(3 downto 0)
        );
    END COMPONENT;

    --Inputs
    SIGNAL clockSource :  std_logic := '0';
    SIGNAL reset :  std_logic := '0';

    --Outputs
    SIGNAL digit :  std_logic_vector(3 downto 0);

BEGIN

    -- Instantiate the Unit Under Test (UUT)
    uut: clock PORT MAP(
        clockSource => clockSource,
        reset => reset,
        digit => digit
    );

    setup : PROCESS
    BEGIN
        reset <= '0';
        wait for 3 ns;
        reset <= '1';
        wait for 3 ns;
        reset <= '0';
        wait;
    END PROCESS;

    generateFreq : PROCESS
    BEGIN
         loop
            clockSource <= '0';
            wait for 1.25 ms;
            clockSource <= '1';
            wait for 1.25 ms;
            clockSource <= '0';
        end loop;
        wait;
    END PROCESS;

END;

Post Revisions:

Changes:

27 July, 2011 @ 3:19Current Revision
Content
<strong>C - micro</strong> <strong>C - micro</strong>
-<pre class="brush:plain"> +<pre class="brush:c">#include &lt;reg66x.h&gt;
-#include <reg66x.h> 
///////////// //////////// ///////////// ////////////
//// PIN DEFINITIONS //// //// PIN DEFINITIONS ////
///////////// //////////// ///////////// ////////////
// Port 0 - in - in from CPLD // Port 0 - in - in from CPLD
#define inDigits P0 #define inDigits P0
// Port 1 - all out - out to CPLD // Port 1 - all out - out to CPLD
sbit outClock = P1^0; sbit outClock = P1^0;
sbit outReset = P1^1; sbit outReset = P1^1;
// Port 2 - all out - out to display // Port 2 - all out - out to display
#define outDisplay P2 #define outDisplay P2
-// Port 3 - in/out - buttons & speaker & CPLD control +// Port 3 - in/out - buttons &amp; speaker &amp; CPLD control
sbit btnStartStop = P3^3; // in sbit btnStartStop = P3^3; // in
sbit outAcknowledge = P3^7;// out sbit outAcknowledge = P3^7;// out
///////////// //////////////// ///////////// ////////////////
//// DECLARE SUBROUTINES //// //// DECLARE SUBROUTINES ////
///////////// //////////////// ///////////// ////////////////
void setupTimer(); void setupTimer();
void setupInputs(); void setupInputs();
void runningLoop(); void runningLoop();
void timerCallback(); void timerCallback();
void digitsCallback(); void digitsCallback();
void controlCallback(); void controlCallback();
void resetCPLD(); void resetCPLD();
///////////// ////////////// ///////////// //////////////
//// DECLARE VARIABLES //// //// DECLARE VARIABLES ////
///////////// ////////////// ///////////// //////////////
-  
int modeState = 0; int modeState = 0;
unsigned char hunths, tenths, seconds, tenSecs; unsigned char hunths, tenths, seconds, tenSecs;
//////////////////////// ////////////////////////
//// PROGRAMME CODE //// //// PROGRAMME CODE ////
//////////////////////// ////////////////////////
void main() { void main() {
setupTimer(); setupTimer();
setupInputs(); setupInputs();
resetCPLD(); resetCPLD();
- runningLoop(); + runningLoop();
} }
void runningLoop() { void runningLoop() {
while(1){ while(1){
outDisplay = tenSecs + 64; outDisplay = tenSecs + 64;
outDisplay = seconds + 128; outDisplay = seconds + 128;
outDisplay = tenths + 192; outDisplay = tenths + 192;
outDisplay = hunths + 0; outDisplay = hunths + 0;
} }
} }
void resetCPLD(){ void resetCPLD(){
outReset = 1; outReset = 1;
outReset = 0; outReset = 0;
return; return;
} }
void setupTimer() { void setupTimer() {
TMOD = 0x01; // M0 = 1 (Timer mode 1 - 16 bit mode) TMOD = 0x01; // M0 = 1 (Timer mode 1 - 16 bit mode)
TL0 = 0xFF; // 400Hz = 2304 delay count, 65535-2304 = 63231 TL0 = 0xFF; // 400Hz = 2304 delay count, 65535-2304 = 63231
TH0 = 0xF6; // TH0 = 0xF6 :: TL0(0xFF) = 0xF6FF = 63231 TH0 = 0xF6; // TH0 = 0xF6 :: TL0(0xFF) = 0xF6FF = 63231
ET0 = 1; // T0 Interrupt enabled. ET0 = 1; // T0 Interrupt enabled.
EA = 1; // Interrupts enabled. EA = 1; // Interrupts enabled.
TR0 = 1; // Begin timer. TR0 = 1; // Begin timer.
-  
P2 = 0x00000000; P2 = 0x00000000;
-  
return; return;
} }
void setupInputs() { void setupInputs() {
EA = 1; // Interrupts enabled. EA = 1; // Interrupts enabled.
IT0 = 1; // Set on falling edge. IT0 = 1; // Set on falling edge.
IT1 = 1; // Set on falling edge. IT1 = 1; // Set on falling edge.
EX0 = 1; // Enable external interrupt 0. EX0 = 1; // Enable external interrupt 0.
EX1 = 1; // Enable external interrupt 1. EX1 = 1; // Enable external interrupt 1.
-  
modeState = 0; modeState = 0;
outAcknowledge = 0; outAcknowledge = 0;
-  
return; return;
} }
//////// INTERRUPT CALLBACKS //////// //////// INTERRUPT CALLBACKS ////////
void timerCallback() interrupt 1 using 2 { void timerCallback() interrupt 1 using 2 {
TR0 = 0; TR0 = 0;
TL0 = 0xFF; // 400Hz = 2304 delay count, 65535-2304 = 63231 TL0 = 0xFF; // 400Hz = 2304 delay count, 65535-2304 = 63231
TH0 = 0xF6; // TH0 = 0xF6 :: TL0(0xFF) = 0xF6FF = 63231 TH0 = 0xF6; // TH0 = 0xF6 :: TL0(0xFF) = 0xF6FF = 63231
TF0 = 0; TF0 = 0;
TR0 = 1; // Begin timer. TR0 = 1; // Begin timer.
outClock =~ outClock; // Invert the clock output pin. outClock =~ outClock; // Invert the clock output pin.
} }
void digitsCallback() interrupt 0 { void digitsCallback() interrupt 0 {
if(modeState == 0){ if(modeState == 0){
- seconds = inDigits & 0x0f; + seconds = inDigits &amp; 0x0f;
}else if(modeState == 1){ }else if(modeState == 1){
- tenSecs = inDigits & 0x0f; + tenSecs = inDigits &amp; 0x0f;
}else if(modeState == 2){ }else if(modeState == 2){
- hunths = inDigits & 0x0f; + hunths = inDigits &amp; 0x0f;
}else if(modeState == 3){ }else if(modeState == 3){
- tenths = inDigits & 0x0f; + tenths = inDigits &amp; 0x0f;
} }
-  
- if(modeState < 3){ + if(modeState &lt; 3){
modeState++; modeState++;
}else{ }else{
modeState = 0; modeState = 0;
} }
-  
outAcknowledge = 1; outAcknowledge = 1;
outAcknowledge = 0; outAcknowledge = 0;
} }
void controlCallback() interrupt 2 { void controlCallback() interrupt 2 {
- TR0 =~ TR0; + TR0 =~ TR0;
-} 
-</pre> +}</pre>
<strong>VHDL - CPLD</strong> <strong>VHDL - CPLD</strong>
-<pre class="brush:plain"> 
-------------- ------------- ------------ ------------- ------------ ------------------- +<pre class="brush: plain">------ ------------ ------------- ------------ ------------- ------------ --------------
--- Company: +-- Company:
--- Engineer: +-- Engineer:
---  
--- Create Date: 12:25:53 03/18/2009  
--- Design Name:  
--- Module Name: clock - Behavioral  
--- Project Name:  
--- Target Devices:  
--- Tool versions:  
--- Description:  
-- --
 +-- Create Date: 12:25:53 03/18/2009
 +-- Design Name:
 +-- Module Name: clock - Behavioral
 +-- Project Name:
 +-- Target Devices:
 +-- Tool versions:
--- Dependencies: +-- Description:
-- --
 +-- Dependencies:
 +--
--- Revision: +-- Revision:
-- Revision 0.01 - File Created -- Revision 0.01 - File Created
--- Additional Comments: +-- Additional Comments:
-- --
------------- ------------- ------------ ------------- ------------ ------------------- ------------- ------------- ------------ ------------- ------------ -------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_ UNSIGNED.ALL; use IEEE.STD_LOGIC_ UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating ---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code. ---- any Xilinx primitives in this code.
--library UNISIM; --library UNISIM;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity clock is entity clock is
Port ( clockSource : in STD_LOGIC; -- clock pulse from micro Port ( clockSource : in STD_LOGIC; -- clock pulse from micro
reset : in STD_LOGIC; -- reset pulse from micro reset : in STD_LOGIC; -- reset pulse from micro
microAck : in STD_LOGIC; -- acknowledgement from micro microAck : in STD_LOGIC; -- acknowledgement from micro
- digit : out STD_LOGIC_VECTOR (3 downto 0); + digit : out STD_LOGIC_VECTOR (3 downto 0);
-- numbers to micro -- numbers to micro
cpldRts : out STD_LOGIC); -- ready to send to micro (ACTIVE LOW) cpldRts : out STD_LOGIC); -- ready to send to micro (ACTIVE LOW)
end clock; end clock;
architecture Behavioral of clock is architecture Behavioral of clock is
signal hunthsCount : std_logic_vector(3 downto 0); signal hunthsCount : std_logic_vector(3 downto 0);
signal tenthsCount : std_logic_vector(3 downto 0); signal tenthsCount : std_logic_vector(3 downto 0);
signal secondCount : std_logic_vector(3 downto 0); signal secondCount : std_logic_vector(3 downto 0);
signal tenSecCount : std_logic_vector(3 downto 0); signal tenSecCount : std_logic_vector(3 downto 0);
signal controlFlag : std_logic_vector(1 downto 0); signal controlFlag : std_logic_vector(1 downto 0);
begin begin
process(reset, clockSource) process(reset, clockSource)
begin begin
if reset = '1' then if reset = '1' then
- hunthsCount <= "0000"; 
- tenthsCount <= "0000"; 
- secondCount <= "0000"; 
- tenSecCount <= "0000"; 
- controlFlag <= "10"; 
- cpldRts <= '1'; 
-elsif microAck = '1' then 
- cpldRts <= '1'; 
-elsif clockSource'event and clockSource = '1' then 
-  
- if controlFlag = "00" then 
- digit <= hunthsCount;+ hunthsCount</pre>
- controlFlag <= "01"; 
- cpldRts <= '0'; 
-  
- elsif controlFlag = "01" then 
- digit <= tenthsCount; 
- controlFlag <= "10"; 
- cpldRts <= '0'; 
-  
- elsif controlFlag = "10" then 
- digit <= secondCount;  
- controlFlag <= "11"; 
- cpldRts <= '0'; 
-  
- elsif controlFlag = "11" then 
- digit <= tenSecCount; 
- controlFlag <= "00"; 
- cpldRts <= '0'; 
-  
- if hunthsCount <= "1000" then 
- hunthsCount <= hunthsCount + "1"; 
-  
- else 
- hunthsCount <= "0000"; 
-  
- if tenthsCount <= "1000" then 
- tenthsCount <= tenthsCount + "1"; 
-  
- else 
- tenthscount <= "0000"; 
-  
- if secondCount <= "1000" then 
- secondCount <= secondCount + "1"; 
-  
- else 
- secondCount <= "0000"; 
-  
- if tenSecCount <= "1000" then 
- tenSecCount <= tenSecCount + "1"; 
-  
- else 
- tenSecCount <= "0000"; 
-  
- end if; 
- end if; 
- end if; 
- end if; 
- end if; 
-  
-end if; 
-end process; 
-end Behavioral; 
-</pre> 
-<strong>VHDL Testbench</strong> 
-<pre class="brush:plain"> 
-------------- ------------- ------------ ------------- ------------ ----------------- 
--- Company:  
--- Engineer: 
--- 
--- Create Date: 11:29:08 03/25/2009 
--- Design Name: clock 
--- Module Name: N:/Coursework/ DigitalSystemS2/stopwatch/ vhdl/counter_ testbench.vhd 
--- Project Name: vhdl 
--- Target Device:  
--- Tool versions:  
--- Description:  
---  
--- VHDL Test Bench Created by ISE for module: clock 
--- 
--- Dependencies: 
---  
--- Revision: 
--- Revision 0.01 - File Created 
--- Additional Comments: 
--- 
--- Notes:  
--- This testbench has been automatically generated using types std_logic and 
--- std_logic_vector for the ports of the unit under test. Xilinx recommends  
--- that these types always be used for the top-level I/O of a design in order  
--- to guarantee that the testbench will bind correctly to the post-implementation  
--- simulation model. 
-------------- ------------- ------------ ------------- ------------ ----------------- 
-LIBRARY ieee; 
-USE ieee.std_logic_1164.ALL; 
-USE ieee.std_logic_ unsigned.all; 
-USE ieee.numeric_std.ALL; 
-ENTITY counter_testbench_vhd IS 
-END counter_testbench_vhd; 
-ARCHITECTURE behavior OF counter_testbench_vhd IS  
- -- Component Declaration for the Unit Under Test (UUT) 
- COMPONENT clock 
- PORT( 
- clockSource : IN std_logic; 
- reset : IN std_logic;  
- digit : OUT std_logic_vector(3 downto 0) 
- ); 
- END COMPONENT; 
- --Inputs 
- SIGNAL clockSource : std_logic := '0'; 
- SIGNAL reset : std_logic := '0'; 
- --Outputs 
- SIGNAL digit : std_logic_vector(3 downto 0); 
-BEGIN 
- -- Instantiate the Unit Under Test (UUT) 
- uut: clock PORT MAP( 
- clockSource => clockSource, 
- reset => reset, 
- digit => digit 
- ); 
- setup : PROCESS 
- BEGIN 
- reset <= '0'; 
- wait for 3 ns; 
- reset <= '1'; 
- wait for 3 ns; 
- reset <= '0'; 
- wait; 
- END PROCESS; 
-  
- generateFreq : PROCESS 
- BEGIN 
- loop 
- clockSource <= '0'; 
- wait for 1.25 ms; 
- clockSource <= '1'; 
- wait for 1.25 ms; 
- clockSource <= '0'; 
- end loop; 
- wait; 
- END PROCESS; 
-END; 
-</pre> 

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